1. Field of the Invention
The present invention relates to three-dimensional (3D) memory devices, and more particularly to channel lines for memory cells in such memory devices.
2. Description of Related Art
High density memory devices are being designed that comprise arrays of flash memory cells, or other types of memory cells. In some examples, the memory cells comprise thin film transistors which can be arranged in 3D architectures.
In one example, a 3D memory device includes a plurality of stacks of poly crystalline active strips separated by insulating material. The active strips can act as bit lines or word lines. The 3D memory device can include a plurality of word lines structures arranged orthogonally over the plurality of stacks of active strips which act as bit lines. Alternatively, the 3D memory device can include a plurality of bit line structures arranged orthogonally over the plurality of stacks of active strips which act as word lines. Memory cells including charge storage structures are formed at cross-points between side surfaces of the active strips in the plurality of stacks and the word lines structures or bit line structures. Channel regions of memory cells are formed in the active material strips that can comprise polysilicon strips. The structure of these polycrystalline channel regions in memory cells can affect performance of 3D memory devices.
3D memory configurations, and other configurations using small dimension memory cells, can present challenges that relate to the performance of individual cells in the memory. It is desirable to improve performance of 3D memory devices.